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| MC74HC165A 8-Bit Serial or Parallel-Input/ Serial-Output Shift Register High-Performance Silicon-Gate CMOS The MC74HC165A is identical in pinout to the LS165. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device is an 8-bit shift register with complementary outputs from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Serial Shift/Parallel Load input is low, the data is loaded asynchronously in parallel. When the Serial Shift/Parallel Load input is high, the data is loaded serially on the rising edge of either Clock or Clock Inhibit (see the Function Table). The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit. http://onsemi.com MARKING DIAGRAMS 16 16 1 PDIP-16 N SUFFIX CASE 648 MC74HC165AN AWLYYWW 1 16 16 1 SO-16 D SUFFIX CASE 751B 1 HC165A AWLYWW * * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 286 FETs or 71.5 Equivalent Gates 16 TSSOP-16 DT SUFFIX CASE 948F 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week HC 165A ALYW 16 1 ORDERING INFORMATION Device MC74HC165AN MC74HC165AD MC74HC165ADR2 MC74HC165ADT MC74HC165ADTR2 Package PDIP-16 SOIC-16 SOIC-16 TSSOP-16 TSSOP-16 Shipping 2000 / Box 48 / Rail 2500 / Reel 96 / Rail 2500 / Reel (c) Semiconductor Components Industries, LLC, 2000 1 July, 2000 - Rev. 4 Publication Order Number: MC74HC165A/D MC74HC165A LOGIC DIAGRAM A B PARALLEL DATA INPUTS C 11 12 13 9 7 QH QH SERIAL DATA OUTPUTS PIN ASSIGNMENT SERIAL SHIFT/ PARALLEL LOAD CLOCK E F G H PIN 16 = VCC PIN 8 = GND QH GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC CLOCK INHIBIT D C B A SA QH D 14 E3 F4 G5 H6 SERIAL SA 10 DATA INPUT SERIAL SHIFT/ 1 PARALLEL LOAD CLOCK 2 CLOCK INHIBIT 15 FUNCTION TABLE Serial Shift/ Parallel Load L H H H H H H H Inputs Clock Inhibit Clock X X L L Internal Stages SA X L H L H H X L X X X A-H a...h X X X X X X X QA a L H L H QB b QAn QAn QAn QAn No Change No Change Output QH h QGn QGn QGn QGn Operation Asynchronous Parallel Load Serial Shift via Clock Serial Shift via Clock Inhibit Inhibited Clock No Clock L L X H L X = don't care QAn - QGn = Data shifted from the preceding stage http://onsemi.com 2 MC74HC165A II II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I III I I I I I II I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIII I II I I I II I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIII I I I II IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I IIII I II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIII II I IIII II I I IIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I II II I I I IIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II I I III II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII II I III II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I IIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* SymbolIIIIIIIIIIIIII Parameter VCC Vin DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0III V V V - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Plastic DIP SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260 _C _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC - 55 0 0 0 + 125 1000 600 500 400 _C ns tr, tf VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit v 85_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.80 1.9 4.4 5.9 Symbol VIH Parameter Test Conditions VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 3.0 4.5 6.0 - 55 to 25_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.80 1.9 4.4 5.9 v 125_C 1.5 2.1 3.15 4.2 0.5 0.9 1.35 1.80 1.9 4.4 5.9 Unit V Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 A VIL Maximum Low-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 A V VOH Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| v 20 A Vin = VIH or VIL V |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 V http://onsemi.com 3 MC74HC165A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I II I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII II II I I I I III I I I I I II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I Guaranteed Limit v 85_C 0.1 0.1 0.1 Symbol VOL Parameter Test Conditions VCC V 2.0 4.5 6.0 3.0 4.5 6.0 6.0 6.0 - 55 to 25_C 0.1 0.1 0.1 v 125_C 0.1 0.1 0.1 Unit V Maximum Low-Level Output Voltage Vin = VIH or VIL |Iout| v 20 A Vin = VIH or VIL |Iout| v 2.4 mA |Iout| v 4.0 mA |Iout| v 5.2 mA 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Iin Maximum Input Leakage Current Vin = VCC or GND Vin = VCC or GND Iout = 0 A 0.1 4 1.0 40 1.0 160 A A ICC Maximum Quiescent Supply Current (per Package) NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). II I III I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I II I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I Guaranteed Limit v 85_C 4.8 17 24 28 Symbol fmax Parameter VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -- - 55 to 25_C 6 18 30 35 v 125_C 4 15 20 24 Unit Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 8) MHz tPLH, tPHL Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH (Figures 1 and 8) 150 52 30 26 175 58 35 30 150 52 30 26 75 27 15 13 10 190 63 38 33 220 70 44 37 190 63 38 33 95 32 19 16 10 225 65 45 38 265 72 53 45 225 65 45 38 110 36 22 19 10 ns tPLH, tPHL Maximum Propagation Delay, Serial Shift/Parallel Load to QH or QH (Figures 2 and 8) ns tPLH, tPHL Maximum Propagation Delay, Input H to QH or QH (Figures 3 and 8) ns tTLH, tTHL Maximum Output Transition Time, Any Output (Figures 1 and 8) ns Cin Maximum Input Capacitance pF NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Package)* 40 pF * Used to determine the no-load dynamic power consumption: P D = CPD VCC2 f + ICC VCC . For load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) http://onsemi.com 4 III I I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I II I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I II I II II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I III I II II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I II I II II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I III I II II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I II I II II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II III I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). TIMING REQUIREMENTS (Input tr = tf = 6 ns) Symbol tr, tf trec tsu tsu tsu tsu tw tw th th th Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit) (Figure 6) Maximum Input Rise and Fall Times (Figure 1) Minimum Pulse width, Serial Shift/Parallel Load (Figure 2) Minimum Pulse Width, Clock (or Clock Inhibit) (Figure 1) Minimum Recovery Time, Clock to Clock Inhibit (Figure 7) Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load (Figure 6) Minimum Hold Time, Clock (or Clock Inhibit) to Input SA (Figure 5) Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs (Figure 4) Minimum Setup Time, Clock to Clock Inhibit (Figure 7) Minimum Setup Time, Input SA to Clock (or Clock Inhibit) (Figure 5) Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load (Figure 4) Parameter http://onsemi.com MC74HC165A 5 VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 - 55 to 25_C 1000 800 500 400 70 27 15 13 70 27 15 13 75 30 15 13 75 30 15 13 75 30 15 13 75 30 15 13 75 30 15 13 5 5 5 5 5 5 5 5 5 5 5 5 Guaranteed Limit v 85_C 1000 800 500 400 90 32 19 16 90 32 19 16 95 40 19 16 95 40 19 16 95 40 19 16 95 40 19 16 95 40 19 16 5 5 5 5 5 5 5 5 5 5 5 5 v 125_C 1000 800 500 400 100 36 22 19 100 36 22 19 110 55 22 19 110 55 22 19 110 55 22 19 110 55 22 19 110 55 22 19 5 5 5 5 5 5 5 5 5 5 5 5 Unit ns ns ns ns ns ns ns ns ns ns ns MC74HC165A PIN DESCRIPTIONS INPUTS A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6) is applied to this pin, data at the Parallel Data inputs are asynchronously loaded into each of the eight internal stages. Clock, Clock Inhibit (Pins 2, 15) Parallel Data inputs. Data on these inputs are asynchronously entered in parallel into the internal flip-flops when the Serial Shift/Parallel Load input is low. SA (Pin 10) Serial Data input. When the Serial Shift/Parallel Load input is high, data on this pin is serially entered into the first stage of the shift register with the rising edge of the Clock. CONTROL INPUTS Serial Shift/Parallel Load (Pin 1) Clock inputs. These two clock inputs function identically. Either may be used as an active-high clock inhibit. However, to avoid double clocking, the inhibit input should go high only while the clock input is high. The shift register is completely static, allowing Clock rates down to DC in a continuous or intermittent mode. OUTPUTS QH, QH (Pins 9, 7) Data-entry control input. When a high level is applied to this pin, data at the Serial Data input (SA) are shifted into the register with the rising edge of the Clock. When a low level Complementary Shift Register outputs. These pins are the noninverted and inverted outputs of the eighth stage of the shift register. http://onsemi.com 6 MC74HC165A SWITCHING WAVEFORMS tr CLOCK OR CLOCK INHIBIT 90% 50% 10% tf VCC GND tw 1/fmax QH OR QH 90% 50% 10% tPLH tPHL QH OR QH tTLH tTHL tw SERIAL SHIFT/ PARALLEL LOAD 50% tPLH 50% 50% tPHL VCC GND Figure 1. Serial-Shift Mode Figure 2. Parallel-Load Mode VALID tr INPUT H tPLH QH OR QH tTLH 90% 50% 10% 90% 50% 10% tPHL SERIAL SHIFT/ PARALLEL LOAD tTHL tf VCC GND INPUTS A-H 50% tsu th VCC GND VCC GND ASYNCHRONOUS PARALLEL LOAD (LEVEL SENSITIVE) Figure 3. Parallel-Load Mode Figure 4. Parallel-Load Mode VALID INPUT SA 50% tsu CLOCK OR CLOCK INHIBIT th 50% VCC GND VCC GND SERIAL SHIFT/ PARALLEL LOAD CLOCK OR CLOCK INHIBIT 50% tsu 50% th VCC GND VCC GND Figure 5. Serial-Shift Mode Figure 6. Serial-Shift Mode TEST POINT CLOCK 2 INHIBITED CLOCK INHIBIT 50% tsu CLOCK 50% trec VCC GND OUTPUT DEVICE UNDER TEST CL* VCC GND *Includes all probe and jig capacitance Figure 7. Serial-Shift, Clock-Inhibit Mode Figure 8. Test Circuit http://onsemi.com 7 MC74HC165A EXPANDED LOGIC DIAGRAM A 11 SERIAL SHIFT/ 1 PARALLEL LOAD SERIAL DATA 10 INPUT SA D QA D QB D QC D QF D QG D QH B 12 C 13 F 4 G 5 H 6 9Q H 7Q H CC CLOCK 2 CLOCK 15 INHIBIT CC CC CC CC CC TIMING DIAGRAM CLOCK CLOCK INHIBIT SA SERIAL SHIFT/ PARALLEL LOAD A B C PARALLEL DATA INPUTS D E F G H QH QH CLOCK INHIBIT MODE PARALLEL LOAD H L H L H L H H HH LL L H H L L H H L L H H L SERIAL-SHIFT MODE http://onsemi.com 8 MC74HC165A PACKAGE DIMENSIONS PDIP-16 N SUFFIX CASE 648-08 ISSUE R -A - 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 6.85 0.250 0.270 3.69 4.44 0.145 0.175 0.39 0.53 0.015 0.021 1.02 1.77 0.040 0.070 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.38 0.008 0.015 2.80 3.30 0.110 0.130 7.50 7.74 0.295 0.305 0 10 0 10 0.51 1.01 0.020 0.040 B 1 8 F S C L -T - H G D 16 PL 0.25 (0.010) M SEATING PLANE K J TA M M SOIC-16 D SUFFIX CASE 751B-05 ISSUE J -A - 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.49 0.35 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 -B - 1 8 P 8 PL 0.25 (0.010) M B M G F K C -T SEATING - PLANE R X 45 D 16 PL 0.25 (0.010) M M J T B S A S http://onsemi.com 9 MC74HC165A PACKAGE DIMENSIONS TSSOP-16 DT SUFFIX CASE 948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U S M TU S V S K K1 16 2X L/2 9 J1 B -U- L PIN 1 IDENT. 1 8 SECTION N-N J N 0.15 (0.006) T U S 0.25 (0.010) M A -V- N F DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ C 0.10 (0.004) -T- SEATING PLANE H D G DETAIL E http://onsemi.com 10 EEE CCC EEE CCC -W- MC74HC165A Notes http://onsemi.com 11 MC74HC165A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 1:00pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 1:00pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, England, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5740-2745 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 12 MC74HC165A/D |
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